1. Field of the Invention
This invention pertains to an apparatus and method of encoding binary bits and more particularly to a method and apparatus for making use of a forward error correction scheme for a reduced number of errors at a given signal-to-noise ration.
2. Background of the Invention
Communication networks using high speed data rates require high signal-to-noise ratios for proper data transmission. Numerous schemes and combinations thereof have been proposed to reduce the number of errors at these given signal-to-noise rations. For example, in U.S. Pat. No. 4,077,021 to Csajka et al. a forward error correcting scheme is described making use of the so-called Viterbi algorithm. In a further development described by the CCITT study group XVII, Contribution No. D180, in October, 1983, entitled TRELLIS-CODED MODULATION SCHEME WITH 8-STATE SYSTEMATIC ENCODER AND 90 SYMMETRY FOR USE IN DATA MODEMS TRANSMITTING 3-7 BITS PER MODULATION INTERVAL a two-dimensional trellis for a quadrature amplitude modulation scheme is disclosed having 90.degree. symmetry which results in a 4 db gain in the signal-to-noise ratio. Typically in forward error coding, redundant bits are added systematically to the data bits so that normally only predetermined transitions from one sequential group of bits (corresponding to bauds) to another are allowed. There is an inherent correlation between these redundant bits over consecutive bauds. At the receiver each baud is tentatively decoded and then analyzed based on past history, and the decoded bits are corrected if necessary. However, it was found that certain types of relatively long error signals, such as for example, low frequency phase jitter, cause a constant phase error in the signal constellation for extended (consecutive baud) periods of time. This type of error prevents or inhibits the correction of the received bits using the schemes described above.